1. Field of the Invention
The present invention generally relates to logic and memory array circuits implemented in integrated circuits with built-in self-testing for logic and memory fault detection and, more particularly, to a method of effectively reducing the length of the shift register (SR) latches for long level-sensitive scan design (LSSD) and generalized scan design (GSD) shift register chains to a relatively small number of latches.
2. Background Description
The level-sensitive scan design (LSSD) and generalized scan design (GSD) test techniques (or simply scan design test techniques) enable testing at all levels of very large scale integrated (VLSI) circuit packaging. The principles of the LSSD technique are described, for example, in U.S. Pat. No. 3,783,254, No. 3,784,907 and No. 3,961,252, all to Eichelberger and assigned to the assignee of this application. The circuit implemented on a chip typically comprises several combinatorial logic blocks, each of which is associated with a storage cell consisting of a latch called a shift register latch (SRL). A single long shift register (SR), termed an LSSD chain, is formed by chaining a number of such cells or SRLs together. Each SRL, which is actually a pair of bistable latches designated L1 and L2, forms a single stage of the shift register.
The L1 latch can be set from two sources by two different clock signals, A and C, applied to clock inputs A and C, with the latter input receiving system clock signals. Latch L1 also has a data input (DI) and a test input called scan data in (SDI). Test patterns consisting of binary bit vectors are applied to the SDI pin of the chip. Latch L2 has a data input connected to one of the outputs of the associated L1 latch and an input that receives B clock signals causing the output data from L1 to be transferred into L2.
The long shift register (SR) referred to above is formed by connecting the output of the L2 latch in the first SRL (forming the first stage of the shift register) to the input of the L1 latch in the next SRL, and so on, down to the last SRL. The test input SDI of the L1 latch in the fist SRL is connected to the SDI pin of the chip, and the output of the L2 latch in the last SRL is connected to an output pin, designated the scan data out (SDO), of the chip. The A, B and C clocks of the SRL are connected to the chip pins so designated. Bits are transferred through the SRL in two steps. A bit applied to the test input SDI of latch L1 is loaded therein by the A clock pulse, and the same bit is obtained at the output of the L2 latch at the occurrence of the B clock pulse. A number of pairs of A and B clock pulses equivalent to the number of SRLs is required in order for a signal applied to the SDI input of a functional element to be transferred to the SDO output thereof. In this mode of operation, clock c is not pulsed.
To test a functional element, a static test called a "flush" test is first performed. To this end, an active potential, for example a high logic level, is applied to the A and B clock inputs (A=B=1) while the C clock input receives a low logic level (C=0). A square pulse is applied to the SDI input of the chain to be tested and is retrieved at the SDO output after a predetermined time interval has elapsed. A typical SR chain may consist of numerous inversion steps. As a result, the data pulse applied to input SDI is obtained at output SDO of the chain after a time interval equal to the accumulated response times of all the SRLs in the chain has elapsed. In addition to providing useful information on the propagation times, the flush test determines whether the LSSD chain is functioning properly.
A dynamic test called a "scan" test is next performed. In this test, the C clock is maintained at a low logic level while pulsing the A and B clocks. The LSSD chain then acts as a shift register. This test serves to establish that the chain is not operating properly if the data pulse applied to the SDI input fails to be transferred to the SDO output when an appropriate number of clock pulses are applied to the A and B clock inputs.
A functional test is then performed in the scan mode. In this test, a test pattern (a series of binary data) is applied to the SDI input and the A and B clocks are pulsed to transfer the test pattern into the SRLs. All the latches in the functional element having thus been initialized, logic data are present on the parallel output pins of the chip. By applying stimuli to the parallel input pins of the chip and pulsing the C clock, a binary vector reflecting some particular state of the combinatorial logic is loaded in the LSSD chain. The output pins and SRL states are then observed to determine if the combinatorial logic is functioning properly as compared to the expected states determined by a computer simulation model.
Typically, one or more array macros are embedded in circuit with most or all of the address and data-in signals provided by SRLs and data-out signals terminating at SRLs. As used herein, a macro is a standard circuit in a circuit library available to the circuit designer. Such standard circuits are replicated many times in the complete circuit implemented in the chip. To properly test these embedded array (EA) macro structures, one usually applies a large number of algorithmic pattern sequences. These patterns are designed to detect faults associated with the whole address space and various operation modes of the macro structure.
The basis for logic built-in self-test (LBIST) and array built-in self-test (ABIST) methodology is to generate product test vectors in order to detect potential faults in the product while the output responses are measured at primary outputs (POs) or captured into a multiple input shift register (MISR). In the diagnostic mode, the strategy is to scan out and observe each response that will be captured into the MISR signature, rather than one scan out of the MISR signature at the end-of-test. The long scan chains will increase test times significantly.
The problem described is surfacing as a major concern in testing. The extensive use of EA macro structures in large LSSD structures and the rapid growth of both the logic and EA densities have pushed existing test systems beyond their capabilities and made test times unacceptable. The problem increases in severity as the number of latches in the SRL extends (in the thousands) to the point where most of the EA test time is consumed in loading and unloading the SRLs rather than testing the array. In addition to the test time problem, most state of the art high speed test systems have limited buffer space and limited algorithmic looping range control to meet the requirements of current product designs.
Several approaches have been considered to solve these problems. One proposed approach is to reconfigure the SRLs such that the latches associated with the EA inputs are placed at the beginning of the SR string, while the latches associated with the EA outputs are placed at the end of the SR string. Then, during the EA test, only a partial shift register load operation is performed. The drawbacks to this approach are that reconfiguring these latches impacts system performance and restricts wiring flexibility. The SR reconfiguration is further restricted when the EA uses the same SR for input and output latching.
Another proposed solution consists of separating the EA specific SRLs into a separate and independent shift register string. The drawback of this approach is that it requires addition inputs and outputs (I/Os) for the shift register input (SRI) and the shift register output (SRO) for each addition shift register string. Yet another proposed solution consists of reconfiguring the SR chain to logically bypass the non-EA SRLs. This approach also requires an additional input to control the scan mode during the EA test and supporting logic to de-gate or bypass the undesired SRLs.